MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 48)

48 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

Group to group constraints establish relative speeds. Here are the constraints that relate

the speeds of ce_2_392b7670_group and ce_3_392b7670_group:

# Group-to-group constraints

TIMESPEC "TS_ce_2_392b7670_group_to_ce_3_392b7670_group" = FROM

"ce_2_392b7670_group" TO "ce_3_392b7670_group" 20.0 ns;

TIMESPEC "TS_ce_3_392b7670_group_to_ce_2_392b7670_group" = FROM

"ce_3_392b7670_group" TO "ce_2_392b7670_group" 20.0 ns;

Port timing requirements can be set in the parameter dialog boxes for gateways. These

requirements are translated into port constraints such as those shown below. In this

example, the 3-bit din input is constrained to operate at its gateway's sample rate

(corresponding to a period of 20 ns). The "FAST" attributes indicate the ports should be

implemented using hardware that reduces delay. The reduction comes at a cost of

increased noise and power consumption.

# Offset in constraints

NET "din(0)" OFFSET = IN : 20.0 : BEFORE "clk";

NET "din(0)" FAST;

NET "din(1)" OFFSET = IN : 20.0 : BEFORE "clk";

NET "din(1)" FAST;

NET "din(2)" OFFSET = IN : 20.0 : BEFORE "clk";

NET "din(2)" FAST;

Selecting Specify IOB Location Constraints for a gateway allows port locations to be

specified. The locations must be entered as a cell array of strings in the box labeled IOB

Pad Locations. Locations are package-specific; in this example a Virtex®-E 2000 in a FG680

package is used. The location constraints for the din bus are provided in the dialog box as

"{'D35', 'B36', 'C35' }". This is translated into constraints in the .xcf (or .ncf) file in the

following way:

# Loc constraints

NET "din(2)" LOC = "D35";

NET "din(1)" LOC = "B36";

NET "din(0)" LOC = "C35";

Clock Handling in HDL

This topic describes how System Generator handles hardware clocks in the HDL it

generates. Assume the design is named <design>, and <design> is an acceptable HDL

identifier. When System Generator compiles the design, it writes a collection of HDL

entities or modules, the topmost of which is named <design>, and is stored in a file

named <design>.vhd/.v.

The “Clock Enables” Multirate Implementation

Clock and clock enables appear in pairs throughout the HDL. Typical clock names are

clk_1, clk_2, and clk_3, and the names of the companion clock enables are ce_1, ce_2, and

ce_3 respectively. The name tells the rate for the clock/clock enable pair; logic driven by

clk_1 and ce_1 runs at the system (i.e., fastest) rate, while logic driven by (say) clk_2 and

ce_2 runs at half the system rate. Clocks and clock enables are not driven in the entity or

module named <design> or any subsidiary entities; instead, they are exposed as top-level

input ports

Of course, there must be a way to generate these clocks and clock enables. System

Generator produces a separate clock wrapper (written to a file named

<design>_cw.vhd/.v) to do this. This wrapper is external to the files described above.

The idea is to make the HDL flexible. In some applications, the files described above are

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