MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 126)

126 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

There are several interesting things to notice about the port interface. First, the component

exposes two clock ports (shown in bold text). The two clock ports are named after the

subsystems from which they are derived (e.g., ss_clk_domaina), and are wired to their

respective subsystem NGC netlist files. Also note that the top-level ports of each

subsystem (e.g., din_a and dout_a) appear as top-level ports in the port interface.

The Multiple Subsystem Generator block does not generate circuitry (e.g., a DCM) to

generate multiple clock sources. You may modify the top-level HDL component to include

the circuitry, or instantiate the top-level HDL as a component in a separate wrapper that

includes the clocking circuitry.

Creating a Top-Level Wrapper

If you decide to create a top-level HDL wrapper for your multi-clock System Generator

design, it should perform the following tasks at a minimum:

• Instantiate the System Generator top-level component along with other wrapper logic

(e.g., a DCM);

• Wire the System generator component to the other logic;

• Create a new top-level port map which supersedes that from the System Generator

component.

The following is an example of making a top-level HDL component to instantiate clocking

circuitry. In this example, you take the output created when the example from the previous

topic is generated using the Multiple Subsystem Generator block. The resulting System

Generator design is called two_async_clks and the top-level HDL component is called

top_wrapper (for the case of VHDL synthesis).

Because the clock lines and main clock enables are inferred, the names of the clocks and

clock enables (with the _ce and _clk suffixes above) are generated automatically by

putting suffixes on the subsystem names from which the clocks are inferred. The other port

names, such as dout_a, are taken directly from the names given to the gateway blocks in

the System Generator design.

An example VHDL top-level wrapper to instantiate the entity two_async_clks, with

deletions made for clarity, is provided below. Note that the wrapper uses a DCM

component to generate the two clocks required by the System Generator design.

----------------------------------------------------------------------

-------

-- top_wrapper.vhd

-- Example Top Level Wrapper

-- This is an example top-level wrapper for instantiating a System

Generator

-- design along with a DCM. In this example, the DCM connects the two

clock

-- inputs of the System Generator block ('two_async_clks') to two

buffered

-- outputs of the DCM, namely, CLK0 and CLKFX. CLK0 is the same

frequency

-- and phase as the input clock, and CLKFX is configured to be twice the

-- frequency of the input clock.

----------------------------------------------------------------------

---------

library IEEE;

library unisim;

use IEEE.std_logic_1164.all;

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