MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 256)

256 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 3: Using Hardware Co-Simulation

co-simulation, you create embedded FIFO-style buffers in the FPGA that can be controlled

directly by a PC.

There are several ways to communicate with a shared FIFO that is embedded inside the

FPGA. The most common approach is to include the other half of the shared FIFO in the

System Generator design. It is also possible to communicate with the shared FIFO using a

C program or MATLAB program. System Generator provides additional blocks that

support vector transfers to and from the FIFO. These blocks will be touched on later in the

tutorial as they play a key role in supporting burst transfers to and from the FPGA.

Adding Buffers to a Design

Having gained an understanding of how shared FIFOs work in hardware, you will now

turn you attention towards building designs that can utilize these buffers for high-speed

vector processing in the FPGA.

Consider the scenario in which you have an FPGA data path that you would like to

accelerate using vector transfers. You need to include input buffer storage in the FPGA that

can store data input samples that are written by the PC. An output buffer is also required

so that the processed data values can be stored while the FPGA waits for the PC to retrieve

them. With these requirements in mind, a From FIFO block is used to implement the input

data buffer and a To FIFO block is used to implement the output data buffer. In the model

shown below, data is written into the data path as soon as it shows up in the input FIFO.

Note that the data path block contains new data (nd) and data valid (vld) flow control

ports. These ports support a simple flow control scheme that determines when new data

enters and valid data leaves the data path. The nd signal is asserted whenever there is data

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 256