MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 389)

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UG640 (v 12.2) July 23, 2010

Timing and Power Analysis Compilation

Timing Analysis Concepts Review

This brief topic is intended for those with little or no knowledge of logic path analysis.

Period and Slack

A timing failure usually means there is a setup time violation in the design. A setup time

violation means that a particular signal cannot get from the output of one synchronous

element to the input of another synchronous element within the requested clock period

and subject to the second synchronous element's setup time requirement. A typical path is

shown in this Synplify schematic:

The path shown is from the Q output of the register on the left (register3) to the D input of

the register on the right (parity_reg). The path goes through two LUTs (lookup tables) that

are configured as 4-input XOR gates. This path has two levels of logic. That means that it

goes through two separate combinational elements (the two LUTs).

The requested period for this path is 10ns. This path easily meets timing. The second of the

two red comma-separated numbers above each logic elements shows the slack for the path.

The slack is the amount of time by which the path 'meets timing'. In this case the slack is

7.79ns. That means that the path could be 7.79ns slower and still meet the 10ns period

requirement. A negative slack value indicates that the path does not meet timing and has

a setup (or hold) time violation.

Path Analysis Example

Let us examine this path in more detail. The first value on the top of register3 is 0.35ns. This

means that the clk-to-out time of the register is 0.35ns, so the data will appear on the Q

output 0.35ns after the rising edge of the clock signal. (The clock signal, not shown, drives

the C inputs of both registers.)

The input of the LUT y_4[0] shows two numbers on each input. The first is the arrival time

of the signal. This value is 0.98ns. This means that the signal arrives at the input 0.98ns

after the rising edge of the clock. Therefore the net delay is (0.98ns-0.35ns)=0.63ns. Any

path delay is divided into net delays and logic delays. In an FPGA, the net delays are

normally the predominant type of delay. This is because the configurable routing fabric of

the FPGA requires that a net traverse many delay-inducing switchboxes in order to reach

its destination.

The path leaves y_4[0] and travels along another net to y[0]. The first of the two values at

the output of y[0] shows the arrival time of the signal at the output of that LUT. This value

is 1.62ns. The signal travels along the final net, incurring a net delay of 0.26ns to arrive at

the D input of parity_reg at 1.88ns after the clock edge. This register has a required setup

time. The setup time for this register is 0.33ns. This means that the signal must arrive at the

D input 0.33ns before the rising edge of the next clock. Therefore the total path requires

(1.88ns+0.33ns)=2.21ns. Subtracted from 10ns, this yields the 7.79ns slack value.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 389