MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 47)

System Generator for DSP User Guide www.xilinx.com 47

UG640 (v 12.2) July 23, 2010

Automatic Code Generation

Constraints Example

The figure below shows a small multirate design and the constraints System Generator

produces for it.

The up sampler doubles the rate, and the down sampler divides the rate by three. Assume

the system clock period is 10 ns. Then the clock periods are 10 ns for the FIR, 20 ns for the

input register, and 30 ns for the output register. The following text describes the constraints

that convey this information.

The lines that indicate the system clock period is10 ns are the following:

# Global period constraint

NET "clk" TNM_NET = "clk_392b7670";

TIMESPEC "TS_clk_392b7670" = PERIOD "clk_392b7670" 10.0 ns HIGH 50 %;

To build timing constraints, the blocks in the design are partitioned into timing groups.

Two blocks are in the same timing group if and only if they run at the same sample rate. In

this design there are three timing groups, corresponding to the three rates. The nature of

constraints dictates that no name is needed for the fastest group. The remaining groups are

named ce_2_392b7670_group and ce_3_392b7670_group; they correspond to periods 20 ns

and 30 ns respectively.

The FIR runs at the system (i.e., fastest) rate and therefore is constrained using the global

period constraint shown above. The logic used to generate clocks always runs at the

system rate and is also constrained to the system rate.

The ce_2_392b7670_group consists of the blocks that operate at half the system rate, i.e., the

input register and the up sampler. Every block in the group is driven by the clock enable

net named ce2_sysgen. The constraints that define the group are the following:

# ce_2_392b7670_group and inner group constraint

Net "ce_2_sg_x0*" TNM_NET = "ce_2_392b7670_group";

TIMESPEC "TS_ce_2_392b7670_group_to_ce_2_392b7670_group" = FROM

"ce_2_392b7670_group" TO "ce_2_392b7670_group" 20.0 ns;

Note: A wildcard character is added to the net name to constrain any additional copies of this net

that may be generated when clock enable logic is replicated. The maximum fanout of a clock enable

net can be controlled in the synthesis tool.

The ce_3_392b7670_group operates at one third the system rate. It contains the down

sampler and the output register, and is defined in a similar manner to the ce2_group.

# ce_3_392b7670_group and inner group constraint

Net "ce_3_sg_x0*" TNM_NET = "ce_3_392b7670_group";

TIMESPEC "TS_ce_3_392b7670_group_to_ce_3_392b7670_group" = FROM

"ce_3_392b7670_group" TO "ce_3_392b7670_group" 30.0 ns;

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 47