120 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
Crossing Clock Domains
System Generator shared memory blocks should be used whenever it is necessary to cross
clock domains. The tool provides several blocks for transferring data across clock domains,
each of which is available in the Xilinx Shared Memory library:
• Shared Memory
• To FIFO / From FIFO
• To Register / From Register
When these shared memory blocks are used to cross clock domains, each set should be
split into a matched pair.
The To FIFO block is put in the domain in which it is to be written. The From FIFO is put
in the domain in which it is to be read. The two blocks are linked by the name of the
Shared memory name parameter. The FIFO is implemented in hardware using the Xilinx
FIFO Generator core. Using FIFO blocks is the safest and easiest-to-use of the three blocks
which cross domains and is the best for high-bandwidth, sequential data transfers.
A pair of Shared Memory blocks is implemented as embedded Xilinx dual-port block
RAM core. The two blocks are linked by the name of the shared memory object. Each
Comments to this Manuals