MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 122)

122 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

The diagram below illustrates the concept of putting domain-crossing blocks into their

own subsystem. When a multiple-domain design is netlisted, System Generator does the

following:

• Creates an HDL file for Domain 0 (on the left), excluding the To FIFO block, and calls

the netlister to create a black-box netlist delivered as an NGC file;

• Creates an HDL file for Domain 1 (on the right), excluding the From FIFO block, and

calls the netlister to create a black-box netlist delivered as an NGC file;

• Invokes the Xilinx CORE Generator™ to produce a core for the FIFO block (middle);

• Creates a top-level HDL wrapper that instantiates three block components.

Step-by-Step Example

This example shows how design hierarchy can be used to partition a System Generator

design into multiple asynchronous clock islands. The example also demonstrates how

Xilinx Shared Memory blocks may be used to communicate between these islands. Lastly,

the example describes how the Multiple Subsystem Generator block can be used to netlist

the complete multi-clock design.

1. From the MATLAB window, change directory to the following:

<ISE_Design_Suite_tree>/sysgen/examples/multiple_clocks/.

2. Open the two_async_clks model from the MATLAB command window, and save it

into a temporary directory of your choosing.

Subsystem hierarchy is used in the example to partition the design into two synchronous

clock domains, to which you refer as domains A and B, that are internally synchronous to

a single clock, but asynchronous relative to each other. The design includes two

subsystems named ss_clk_domainA and ss_clk_domainB, which include logic

associated with clock domains, A and B, respectively. The blocks inside the

ss_clk_domainA subsystem operate in clock domain A while all blocks inside the

ss_clk_domainB subsystem operate in a second clock domain, B.

The asynchronous islands in the example communicate with one another via a shared

memory interface implemented using a pair of Xilinx Shared Memory

blocks. The two

Shared Memory blocks are distributed so that one block resides in domain

ss_clk_domainA and the other resides in domain ss_clk_domainB. Both blocks

specify the same shared memory object name, bram_iface. This allows the Shared

Memory blocks to access a common address space during simulation. Note that in the

diagram there is no physical connection shown between the two shared memory halves.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 122