332 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
SysgenBlockDescriptor Methods
Method Description
setTopLevelLanguage(language) Declares language for the top-level entity (or
module) of the black box. language should be
'VHDL' or 'Verilog'.
setEntityName(name) Sets name of the entity or module.
addSimulinkInport(pname) Adds an input port to the black box. pname tells the
name the port should have.
addSimulinkOutport(pname) Adds an output port to the black box. pname tells
the name the port should have.
setSimulinkPorts(in,out) Adds input and output ports to the black box. in
(respectively, out) is a cell array whose element tell
the names to use for the input (resp., output) ports.
addInoutport(pname) Adds a bi-directional port to the black box. pname
specifies the name the port should have. Bi-
directional ports can only be added during the
'config_netlist_interface' phase of configuration.
tagAsCombinational() Indicate that the block has a combinational path (i.e.,
direct feedthrough) from an input port to an output
port.
addClkCEPair(clkPname, cePname,
rate)
Defines a clock/clock enable port pair for the block.
clkPname and cePname tell the names for the clock
and clock enable ports respectively. rate, a double,
tells the rate at which the port pair runs. The rate
must be a positive integer. Note the clock
(respectively, clock enable) name must contain the
substring clk (resp., ce). The names must be parallel
in the sense that the clock enable name is obtained
from the clock name by replacing clk with ce.
port(name) Returns the SysgenPortDescriptor that matches the
specified name.
inport(indx) Returns the SysgenPortDescriptor that describes a
given input port. indx tells the index of the port to
look for, and should be between 1 and
numInputPorts.
outport(indx) Returns the SysgenPortDescriptor that describes a
given output port. indx tells the index of the port to
look for, and should be between 1 and
numOutputPorts.
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