MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 24)

24 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

In the System Generator portion of a Simulink model, every signal must be sampled.

Sample times may be inherited using Simulink's propagation rules, or set explicitly in a

block customization dialog box. When there are feedback loops, System Generator is

sometimes unable to deduce sample periods and/or signal types, in which case the tool

issues an error message. Assert blocks must be inserted into loops to address this problem.

It is not necessary to add assert blocks at every point in a loop; usually it suffices to add an

assert block at one point to “break” the loop.

Note:

Simulink can display a model by shading blocks and signals that run at different rates with

different colors (Format > Sample Time Colors in the Simulink pulldown menus). This is often useful

in understanding multirate designs

Bit-True and Cycle-True Modeling

Simulations in System Generator are bit-true and cycle-true. To say a simulation is bit-true

means that at the boundaries (i.e., interfaces between System Generator blocks and non-

System Generator blocks), a value produced in simulation is bit-for-bit identical to the

corresponding value produced in hardware. To say a simulation is cycle-true means that at

the boundaries, corresponding values are produced at corresponding times. The

boundaries of the design are the points at which System Generator gateway blocks exist.

When a design is translated into hardware, Gateway In (respectively, Gateway Out) blocks

become top-level input (resp., output) ports.

Timing and Clocking

Discrete Time Systems

Designs in System Generator are discrete time systems. In other words, the signals and the

blocks that produce them have associated sample rates. A block’s sample rate determines

how often the block is awoken (allowing its state to be updated). System Generator sets

most sample rates automatically. A few blocks, however, set sample rates explicitly or

implicitly.

Note:

For an in-depth explanation of Simulink discrete time systems and sample times, consult the

Using Simulink reference manual from the MathWorks, Inc.

A simple System Generator model illustrates the behavior of discrete time systems.

Consider the model shown below. It contains a gateway that is driven by a Simulink source

(Sine Wave), and a second gateway that drives a Simulink sink (Scope).

The Gateway In block is configured with a sample period of one second. The Gateway Out

block converts the Xilinx fixed-point signal back to a double (so it can analyzed in the

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 24