140 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
Tutorial Example: Using ChipScope Pro Analyzer with JTAG Hardware
Co-Simulation
Design Description
The following Simulink design model is used to demonstrate an integrated design flow
between ChipScope Pro Analyzer and JTAG Hardware Co-simulation. The model contains
a DDS Compiler block and a ChipScope block. The phase_in input port of the DDS
Compiler block is accumulated phase variations, which are in turn used to adjust sine and
cosine output waveforms. These outputs are then internally captured by ChipScope Pro
Analyzer in real time.
Setup the SP601 Hardware Co-Simulation Platform
Setup the SP601 Platform for JTAG Hardware Co-Simulation as described in the topic
Installing an SP601/SP605 Board for JTAG Hardware Co-Simulation.
Generate a Bitstream File
1. Open <sysgen_path>/examples/chipscope/example2/chipscope_ex2.mdl and
generate a netlist targeting SP601 JTAG
2. Save the current Simulink model as chipscope_ex2_hwcs.mdl
3. Replace all the Simulink blocks with the JTAG HWCS block that you just generated
except for input and output gateways
4. Add a Simulink Slider Gain block to attenuate phase inc/dec changes and your model
should look similar to the figure below:
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