System Generator for DSP User Guide www.xilinx.com 207
UG640 (v 12.2) July 23, 2010
Designing with Embedded Processors and Microcontrollers
9. Use the Remove button to remove unused IO Devices and Internal Peripherals under
Processor 1 at the right-hand side of the screen and only keep RS232_Uart_1,
dlmb_cntlr, and ilmb_cntr as shown in the figure below. Click Next.
10. Click Next in the Cache configuration screen and press OK on Timing closure
Warning.
11. Click Next in the Application configuration screen
12. Click Finish in the Summary screen
13. Click OK in The Next Step screen and close the XPS application
Step 3 Import the Embedded System into the Sysgen Design and Generate a
Hardware Co-Simulation Block
General Flow for this Exercise
You have just completed the process of creating and configuring an embedded system for
a Xilinx FPGA. This embedded system is now ready to be incorporated into a Sysgen
design – fir_example_mb.mdl
1. Switch to Sysgen and open the file fir_example_mb.mdl
Note:
This may take up to 3 minutes the first time since Sysgen will call PartGen in order to populate
the devices in the Sysgen token.
Note: Change the Simulink Solver on this model to ‘ode45’ or you will get the following warning:
Warning: The model 'fir_example_mb' does not have continuous states, hence Simulink is using the
solver 'VariableStepDiscrete' instead of solver 'ode45'
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