MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 27)

System Generator for DSP User Guide www.xilinx.com 27

UG640 (v 12.2) July 23, 2010

System-Level Modeling in System Generator

The Clock Enables Option

When System Generator compiles a model into hardware with the Clock Enable option

selected, System Generator preserves the sample rate information of the design in such a

way that corresponding portions in hardware run at appropriate rates. In hardware,

System Generator generates related rates by using a single clock in conjunction with clock

enables, one enable per rate. The period of each clock enable is an integer multiple of the

period of the system clock.

Inside Simulink, neither clocks nor clock enables are required as explicit signals in a

System Generator design. When System Generator compiles a design into hardware, it

uses the sample rates in the design to deduce what clock enables are needed. To do this, it

employs two user-specified values from the System Generator block: the Simulink system

period and FPGA clock period. These numbers define the scaling factor between time in a

Simulink simulation, and time in the actual hardware implementation. The Simulink

system period must be the greatest common divisor (gcd) of the sample periods that

appear in the model, and the FPGA clock period is the period, in nanoseconds, of the

system clock. If p represents the Simulink system period, and c represents the FPGA

system clock period, then something that takes kp units of time in Simulink takes k ticks of

the system clock (hence kc nanoseconds) in hardware.

To illustrate this point, consider a model that has three Simulink sample periods 2, 3, and

4. The gcd of these sample periods is 1, and should be specified as such in the Simulink

System Period field for the model. Assume the FPGA Clock Period is specified to be 10ns.

With this information, the corresponding clock enable periods can be determined in

hardware.

In hardware, we refer to the clock enables corresponding to the Simulink sample periods 2,

3, and 4 as CE2, CE3, and CE4, respectively. The relationship of each clock enable period to

the system clock period can be determined by dividing the corresponding Simulink

sample period by the Simulink System Period value. Thus, the periods for CE2, CE3, and

CE4 equal 2, 3, and 4 system clock periods, respectively. A timing diagram for the example

clock enable signals is shown below:

The Hybrid DCM-CE Option

If the implementation target is an FPGA with a Digital Clock Manager (DCM), you can

choose to drive the clock tree with a DCM. The DCM option is desirable when high fanout

on clock enable nets make it difficult to achieve timing closure.

System Generator instantiates the DCM in a top-level HDL clock wrapper and configures

the DCM to provide up to

three clock ports at different rates for Virtex®-4 and Virtex®-5 and

up to two clock ports for Spartan-3A DSP

. If the design has more clock ports than the DCM

can support, the remaining clocks are supported with the CE (clock enable) configuration.

The mapping of rates to the DCM outputs is done according to the following priority

scheme:

CLK0 > CLK2x > CLKdv > CLKfx. The DCM supports the higher clock rates first.

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