MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 233)

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UG640 (v 12.2) July 23, 2010

Board-Specific I/O Ports

Note: The clocking options available to a hardware co-simulation block depend on the FPGA board

being used (i.e., some boards may not support a free-running clock source, in which case it is not

available as a dialog box parameter).

Board-Specific I/O Ports

FPGA boards often include a variety of on-board devices (e.g., external memory, analog to

digital converters, etc.) that the FPGA can communicate with. For a variety of reasons, it

may be useful to form connections to these components in your System Generator models,

and to use these components during hardware co-simulation. For example, if your board

includes external memory, you may want to define the control and interface logic to this

memory in your System Generator design, and use the physical memory during hardware

co-simulation.

You can interface to these types of components by including board-specific I/O ports in

your System Generator models. A board-specific port is a port that is wired to an FPGA

pad when the model is compiled for hardware co-simulation. Note that this type of port

differs from standard co-simulation ports that are controlled by a corresponding port on a

hardware co-simulation block.

A board-specific I/O port is implemented using special non-memory mapped gateway blocks

that tell System Generator to wire the signals to the appropriate FPGA pins when the

model is compiled into hardware. To connect a System Generator signal to a board-specific

port, connect the appropriate wire to the special gateway (in the same way as is done for a

traditional gateway).

Non-memory mapped gateways that are common to a specific device are often packaged

together in a Simulink subsystem or library. The XtremeDSP Development Kit, for

example, provides a library of external device interface subsystems, including analog to

digital converters, digital to analog converters, LEDs, and external memory. The interface

subsystems are constructed using Gateways that specify board-specific port connections.

These subsystems are treated like other System Generator subsystems during simulation

(i.e., they perform double precision to Xilinx fixed-type conversions). When System

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 233