MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 329)

System Generator for DSP User Guide www.xilinx.com 329

UG640 (v 12.2) July 23, 2010

Black Box Configuration M-Function

The SysgenBlockDescriptor object provides Boolean member variables

inputTypesKnown and inputRatesKnown that tell whether the port types and rates

have been propagated to the block. If you are setting dynamic output port types or rates

based on input port configurations, the configuration calls should be nested inside

conditional statements that check that values of inputTypesKnown and

inputRatesKnown.

The following code shows how to set the width of a dynamic output port dout to have the

same width as input port din:

if (this_block.inputTypesKnown)

dout.setWidth(this_block.port('din').width);

end

Setting dynamic rates works in a similar manner. The code below sets the sample rate of

output port dout to be twice as slow as the sample rate of input port din:

if (this_block.inputRatesKnown)

dout.setRate(this_block.port('din').rate*2);

end

Black Box Clocking

In order to import a multirate module, you must tell System Generator information about

the module's clocking in the configuration M-function. System Generator treats clock and

clock enables differently than other types of ports. A clock port on an imported module

must always be accompanied by a clock enable port (and vice versa). In other words, clock

and clock enables must be defined as a pair, and exist as a pair in the imported module.

This is true for both single rate and multirate designs.

Note:

Although clock and clock enables must exist as pairs, System Generator drives all clock ports

on your imported module with the FPGA system clock. The clock enable ports are driven by clock

enable signals derived from the FPGA system clock.

SysgenBlockDescriptor provides a method, addClkCEPair, which allows you to define

clock and clock enable information for a black box. This method accepts three parameters.

The first parameter defines the name of the clock port (as it appears in the module). The

second parameter defines the name of the clock enable port (also as it appears in the

module).

The port names of a clock and clock enable pair must follow the naming conventions

provided below:

• The clock port must contain the substring clk

• The clock enable must contain the substring ce

• The strings containing the substrings clk and ce must be the same (e.g., my_clk_1

and my_ce_1).

The third parameter defines the rate relationship between the clock and the clock enable

port. The rate parameter should not be thought of as a Simulink sample rate. Instead, this

parameter tells System Generator the relationship between the clock sample period, and

the desired clock enable sample period. The rate parameter is an integer value that defines

the ratio between the clock rate and the corresponding clock enable rate.

For example, assume you have a clock enable port named ce_3 that would like to have a

period three times larger than the system clock period. The following function call

establishes this clock enable port:

addClkCEPair('clk_3','ce_3',3);

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