System Generator for DSP User Guide www.xilinx.com 385
UG640 (v 12.2) July 23, 2010
EDK Export Tool
In another model (shown below), you create corresponding input gateways. You set this
up as a TARGET bus giving the bus interface the same Bus Standard myVideoBus. XPS
will use the Bus Standard name to match different bus interfaces. XPS will then connect the
outputs to the inputs with the same Bus Interface Names.
You export this pcore to the XPS project. When these two pcores are used in the same XPS
project, XPS will detect that they have compatible buses and will allow you to connect
them if you wish.
Export as Pcore to EDK
When a System Generator design is exported to the EDK, the name of the pcore (processor
core) has the postfix "_plbw" appended to the model name if a PLB v6.4 bus is specified.
For example, when a model called mul_accumulate is exported to the EDK, it will be called
mul_accumulate_plbw on the EDK side. If Fast Simplex Link is specified, the postfix
“_sm” is appended to the model name.
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