MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 327)

System Generator for DSP User Guide www.xilinx.com 327

UG640 (v 12.2) July 23, 2010

Black Box Configuration M-Function

accessing the port objects that are associated with it. For example, the following method

retrieves the port named din on the this_block descriptor:

Accessing a SysgenPortDescriptor object:

din = this_block.port('din');

In the above code, an object din is created and assigned to the descriptor returned by the

port function call.

SysgenBlockDescriptor also provides methods, inport and outport, that return a port

object given a port index. A port index is the index of the port (in the order shown on the

block interface) and is some value between 1 and the number of input/output ports on the

block. These methods are useful when you need to iterate through the block's ports (e.g.,

for error checking).

Configuring Port Types

SysgenPortDescriptor provides methods for configuring individual ports. For example,

assume port dout is unsigned, 12 bits, with binary point at position 8. The code below

shows one way in which this type can be defined.

dout = this_block.port('dout');

dout.setWidth(12);

dout.setBinPt(8);

dout.makeUnsigned();

The following also works:

dout = this_block.port('dout');

dout.setType('Ufix_12_8');

The first code segment sets the port attributes using individual method calls. The second

code segment defines the signal type by specifying the signal type as a string. Both code

segments are functionally equivalent.

The black box supports HDL modules with 1-bit ports that are declared using either single

bit port (e.g., std_logic) or vectors (e.g., std_logic_vector(0 downto 0)) notation. By default,

System Generator assumes ports to be declared as vectors. You may change the default

behavior using the useHDLVector method of the descriptor. Setting this method to true

tells System Generator to interpret the port as a vector. A false value tells System

Generator to interpret the port as single bit.

dout.useHDLVector(true); % std_logic_vector

dout.useHDLVector(false); % std_logic

Note: The Configuration Wizard automatically sets the port types when it generates a configuration

M-function.

Configuring Bi-Directional Ports for Simulation

Bi-directional ports (or inout ports) are supported only during the generation of the HDL

netlist, that is, bi-directional ports will not show up in the System Generator diagram. By

default, bi-directional ports will be driven with 'X' during simulation. It is possible to

overwrite this behavior by associating a data file to the port. Be sure to guard this code

since bi-directional ports can only be added to a block during the config_netlist_interface

phase.

(strcmpi(this_block.getConfigPhaseString,'config_netlist_interface'))

bidi_port = this_block.port('bidi');

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