MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 378)

378 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 5: System Generator Compilation Types

HDL Netlist Compilation

System Generator uses the HDL Netlist compilation type as the default generation target.

More details regarding the HDL Netlist compilation flow can be found in the sub-topic

titled Compilation Results.

As shown below, you may select HDL netlist compilation by left-clicking the Compilation

submenu control on the System Generator block dialog box, and select the HDL Netlist

target.

NGC Netlist Compilation

The NGC Netlist compilation target allows you to compile your design into a standalone

Xilinx NGC binary netlist file. The NGC netlist file that System Generator produces

contains the logical and optional constraint information for your design. This means the

HDL, cores, and constraints file information corresponding to a System Generator design

are self-contained within a single file.

If you have chosen to include clock wrapper logic in your design, the netlist file is saved as

<design>_cw.ngc. Otherwise, the file is saved as <design>.ngc. Here <design> is

derived from the portion of the design being compiled. This file can be used as a module in

a larger design, or as input to NGDBuild when the netlist constitutes the complete design.

For an example showing how a System Generator design can be used as a component in a

larger design, refer to the topic titled Importing a System Generator Design into a Bigger

System.

The NGC compilation target generates an HDL component instantiation template that

makes it easy to include your System Generator design as a component in a larger design.

For VHDL compilation, the template is saved as <design>_cw.vho when the clock

wrapper is included. Otherwise it is saved as <design>.vho . Alternatively, a .veo

extension is used for Verilog compilation. The instantiation template is saved in the

design's target directory.

System Generator produces the NGC netlist file by performing the following steps during

compilation:

1. Runs the selected synthesis tool to produce a lower-level netlist. The type of netlist

(e.g., EDIF for Synplify or Synplify Pro, NGC for XST) depends on which synthesis tool

is chosen for compilation.

Note:

Note: IO buffers are not inserted in the design during synthesis.

2. Combines synthesis results, core netlists, black box netlists, and optionally the

constraints files into a single NGC file.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 378