MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 390)

390 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 5: System Generator Compilation Types

Clock Skew and Jitter

The net delay values shown here are estimates provided by Synplify. The synthesizer

doesn't know the actual net delay values because these are not determined until after the

place & route process. An actual path contains other variables which must be accounted

for, including clock skew and clock jitter. Clock skew is the amount of time between clock

arrival at the source and destination synchronous elements. Clock jitter is a variation of the

clock period from cycle to cycle. Jitter is created by the DCMs (digital clock managers) and

by other means. The timing analysis is carried out with worst-case values for the given

part's delay values, jitter, skew, and temperature derating.

Timing Analyzer Features

Observing the Slow Paths

Clicking on the Slow Paths icon displays the paths with the least slack for each timing

constraint. An example is shown below:

The top section of the display shows a list of slow paths, while the bottom section of the

display shows details of the path that is selected. The elements of this display are explained

here:

• Timing Constraint: You may opt to view the paths from all timing constraints or just a

single constraint. A typical System Generator design has but a single timing

constraint which defines the period of the system clock. This is the constraint shown

in this example. TS_clk_a5c9593d is the name of the constraint; the (sometimes

confusing) suffix is a hash meant to make the identifier unique when multiple System

Generator designs are used as components inside a larger design. The timing group

clk_a5c9593 is a group of synchronous logic, again with a hash suffix. The group in

this case contains all the synchronous elements in the design. The period of the clock

here is 10ns with a 50% duty cycle.

• Source: The System Generator block that drives the path.

• Destination: This is the System Generator block that is the terminus of the path.

• Slack: The slack for this particular path. See the topic entitled Period and Slack for

more details.

• Delay (Path): The delay of the entire path, including the setup time requirement.

• % Route Delay: This is the percentage of the path that is consumed by routing (net)

delay. The remainder portion of the path is consumed by logic delay.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 390