MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 317)

System Generator for DSP User Guide www.xilinx.com 317

UG640 (v 12.2) July 23, 2010

Supporting New Boards through JTAG Hardware Co-Simulation

Note: A subsystem (as shown below) is a convenient place to store the gateway out and convert

block pairs.

Providing Your Own Top Level

When a model is compiled for JTAG hardware co-simulation, System Generator produces

a generic top-level HDL entity for the design. This entity instantiates the logic required by

the model and the interfacing logic required for JTAG hardware co-simulation.

Sometimes your board may have a special requirement that precludes you from using this

generic top level. For example, your board may have components that rely on clocks that

are generated by a DCM that resides in the board's FPGA. In these situations, System

Generator allows you to use your own top-level netlist when it compiles the model into

hardware.

Note:

If you choose to use your own top-level component, you must provide a previously

synthesized version (.ngc, .edf, .edn) to System Generator.

Note: Your top-level component must instantiate the generic JTAG hardware co-simulation top-level

component. The component instantiation must include the required clocking signals, plus any board-

specific I/O ports your board may support. An example component instantiation is provided below:

component jtagcosim_top port (

-- required clocking ports

sys_clk : in std_logic;

cosim_clk : out std_logic;

sys_clk_buf : out std_logic;

-- board specific ports

adc1_d : in std_logic_vector(13 downto 0);

dac1_d : out std_logic_vector(13 downto 0);

dac1_div0 : out std_logic;

dac1_div1 : out std_logic;

dac1_mod0 : out std_logic;

dac1_mod1 : out std_logic;

dac1_reset : out std_logic

);

end component;

You may specify your own top-level netlist in yourboard_postgeneration.m as

follows:

params.vendor_toplevel = 'yourboard_toplevel';

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 317