MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 395)

System Generator for DSP User Guide www.xilinx.com 395

UG640 (v 12.2) July 23, 2010

Timing and Power Analysis Compilation

about every net and logic delay, clock skew, and clock uncertainty. The box at the bottom

left of this display shows the path name of the timing report.

Improving Failing Paths

"Now I have information about my failing paths; but what do I do now?" you may ask

yourself. This is the trick for which there is no simple answer, and this is where you may

need to delve into the lower-level aspects of FPGA design.

In general, steps that may be taken to meet timing are, in this order:

1. Change the source design. Just about any timing problem can be solved by changing

the source design and this is the easiest way to speed up the circuit. Unfortunately, this

is often the last step taken by designers, who often look for a quick solution such as

using a faster part. The source design may be changed in several ways:

a. Pipelining. This is the surest way to improve speed, but may also be tricky.

Adding pipelining registers increases latency. For designs with feedback, this may

require great care since portions of the design may require pipeline rebalancing.

See the later example for more details on pipelining.

b. Parallelization. This is probably the second most-important improvement you can

make. Do you have a FIR filter that won't operate at the correct speed? You can use

two FIR filters in parallel, each operating at half-rate, and interleave the outputs.

This is the classic speed/area tradeoff.

c. Retiming. This involves taking existing registers and moving them to different

points within the combinational logic to rob from Peter to pay Paul, so to speak.

This works if, to stretch the maxim, Paul is bereft of slack, while Peter has a surfeit.

Some synthesis tools can perform a degree of retiming automatically.

d. Replication. Replication of registers or buffers increases the amount of logic but

reduces the fanout on the replicated objects. This decreases the capacitance of the

net and reduces net delay. The replicated registers may also be floorplanned to

place them closer to the logic groups they drive. Replication is often performed

automatically by the tools and manual replication is not a common practice in a

high-level design environment like System Generator.

e. Shannon Expansion. This method involves replicating the faster logic in a critical

path in order to remove dependencies on slower logic. This is sometimes done

automatically by the synthesizer.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 395