MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 147)

System Generator for DSP User Guide www.xilinx.com 147

UG640 (v 12.2) July 23, 2010

Integrating a Processor with Custom Logic

Hardware Generation

The EDK Processor block supports two modes of operation: EDK pcore generation and

HDL netlisting. The different modes of operation are illustrated below and can be chosen

from a list-box in the EDK Processor block's GUI.

EDK pcore Generation Mode

The Xilinx Embedded Development Kit (EDK) allows peripherals to be attached to

processors created within the EDK. These peripherals can be packaged as pcores. Each

pcore contains a collection of files describing the peripheral's hardware description,

software drivers, bus connectivity and documentation.

When set in EDK-pcore-generation mode and used with the EDK Export Tool (selected via

the System Generator token), System Generator is able to create a pcore from the given

System Generator model. The figure above shows the part of the model that is created as a

pcore. When set in this mode, the assumption is that the MicroBlaze™ processor added to

the model is just a place-holder. Its actual implementation will be filled in by the EDK

when the peripheral is finally added into an EDK project. As such, the pcore that is created

consists of the custom logic, the generated memory map and virtual connections to the

custom logic, and the bus adaptor.

HDL Netlist Mode

An EDK processor can also be brought into a System Generator model when HDL

netlisting mode is selected. The EDK Processor block can be set to HDL netlisting mode

only when an EDK project is supplied to the block. When in HDL netlisting mode, the

processor described in the EDK project will be imported into System Generator as a black

box. The supplied EDK project is also augmented with the bus interfaces necessary to

connect the System Generator memory map to the processor. During netlisting, the

MicroBlaze™ processor and the generated memory-map hardware are both netlisted into

hardware.

Hardware Co-Simulation

Currently the EDK Processor block provides hardware-based simulation through

hardware co-simulation. The creation of a Hardware Co-Simulation block follows the

standard co-simulation flow described in the topic Using Hardware Co-Simulation. The

only difference is how top-level ports of the imported XPS project are treated.

When an XPS project is imported into System Generator, the import wizard assumes that

all the ports are well constrained and applies that given constraint on the ports during the

creation of the Hardware Co-Simulation block. That is to say, if the top-level entity of the

XPS system contains ports that connect to pads on the FPGA, when compiling a Hardware

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 147