MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 36)

36 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

8. After the simulation is finished, you should be able to observe the simulation

waveforms as shown in the figure below:

Summary

When you select the Expose Clock Ports option, System Generator automatically infers the

correct clocks from the design rates and exposes the clock ports in the top-level wrapper.

The clock rates are determined by the same methodology when you use the Clock Enables

option. You can now drive the exposed clock ports from an external synchronous clock

source.

Synchronization Mechanisms

System Generator does not make implicit synchronization mechanisms available. Instead,

synchronization is the responsibility of the designer, and must be done explicitly.

Valid Ports

System Generator provides several blocks (in particular, a FIFO) that can be used for

synchronization. Several blocks provide input (respectively, output) ports that specify

when an input (resp., output) sample is valid. Such ports can be chained, affording a

primitive form of flow control. Blocks with such ports include the FFT, FIR, and Viterbi.

Indeterminate Data

Indeterminate values are common in many hardware simulation environments. Often they

are called “don’t cares” or “Xs”. In particular, values in System Generator simulations can

be indeterminate. A dual port memory block, for example, can produce indeterminate

results if both ports of the memory attempt to write the same address simultaneously.

What actually happens in hardware depends upon effectively random implementation

details that determine which port sees the clock edge first. Allowing values to become

indeterminate gives the system designer greater flexibility. Continuing the example, there

is nothing wrong with writing to memory in an indeterminate fashion if subsequent

processing does not rely on the indeterminate result.

HDL modules that are brought into the simulation through HDL co-simulation are a

common source for indeterminate data samples. System Generator presents indeterminate

values to the inputs of an HDL co-simulating module as the standard logic vector 'XXX . .

. XX'.

Indeterminate values that drive a Gateway Out become what are called NaNs. (NaN

abbreviates “not a number”.) In a Simulink scope, NaN values are not plotted. Conversely,

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 36