MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 359)

System Generator for DSP User Guide www.xilinx.com 359

UG640 (v 12.2) July 23, 2010

Black Box Examples

17. Examine the scope output after the simulation has completed. When the Simulation

Mode was set to Inactive, the Output Signal scope displayed constant zero. Notice the

waveform is no longer zero. Instead, Output Signal shows the results from the

ModelSim simulation.

Importing a Verilog Module

This example demonstrates how Verilog black boxes can be used in System Generator and

co-simulated using ModelSim. Verilog modules are imported the same way VHDL

modules are imported. For more information on how this is done, seethe topics Black Box

Configuration Wizard and Black Box Configuration M-Function. System Generator

provides all of the code that is needed to incorporate Verilog black boxes, both to generate

hardware and to co-simulate HDL. System Generator also allows Verilog black boxes to be

parameterized. This example demonstrates all of these capabilities. The files for this

example are contained in the following directory:

<ISE_Design_Suite_tree>/sysgen/examples/black_box/example4.

The files are:

• black_box_ex4.mdl – A Simulink model with two black boxes, one using VHDL

and the other using Verilog.

• word_parity_block.vhd – The VHDL for the combinational portion of the state

machine seen in word parity example presented above. This is a purely combinational

(stateless) block that computes the parity of each input word and outputs the parity

bit. It has been parameterized with a generic so that it can accept any input type (see

the description of dynamic black boxes for a discussion of generics).

• word_parity_block_config.m – The configuration M-function for the VHDL

black box, including the generic setting. The M-function tags this block as

combinational so that it simulates correctly in Simulink.

• shutter.v – The Verilog for a simple synchronous latch. The code has been

parameterized so that the input port din can have arbitrary width.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 359