System Generator for DSP User Guide www.xilinx.com 151
UG640 (v 12.2) July 23, 2010
Integrating a Processor with Custom Logic
There is a Shared Memory Settings session in the API documentation, which lists the settings
of the available shared memories contained by the System Generator peripheral as shown
in the following figure.
Writing a Software Program
You should follow the Xilinx SDK flow to create a software application project and write
software to drive the System Generator peripheral. In the HDL netlist mode, you can
choose a sample application to customize for the System Generator peripheral as shown in
the figure below.
In the API documentation, a number of example code snippets are provided to perform
read/write operations. These code snippets are detailed in the following text.
Accessing "From Register" and "To Register" shared memories
Single-Word Writes
The following code snippet writes a value to the "To Register" shared memory named
"toreg".
uint32_t value;
xc_iface_t *iface;
xc_to_reg_t *toreg;
// initialize the software driver, assuming the Pcore device ID is 0
xc_create(&iface, &SG_PLBIFACE_ConfigTable[0]);
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