MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 254)

254 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 3: Using Hardware Co-Simulation

Frame-Based Acceleration using Hardware Co-Simulation

With the tremendous growth in programmable device size and computational power,

lengthy simulation times have become an expected, yet undesirable part of life for most

engineers. Depending on the design size and complexity, the required simulation time can

be quite large, sometimes on the order of days to run to completion. This problem is

exacerbated by the fact that most systems must be simulated many times before the design

is considered functional and ready for deployment. Fortunately, System Generator for DSP

provides hardware co-simulation interfaces that allow you to dramatically accelerate

simulation speeds of your FPGA designs.

There are several factors that influence exactly how much acceleration can be gained by

using hardware co-simulation. These considerations include the size of the design, the

number of ports on the model, and the hardware over-sampling rate. Under normal

operation, the PC communicates with the FPGA during each Simulink simulation cycle.

These software / hardware transactions often involve significant overhead and can end up

being the limiting factor in simulation performance. Also of importance is the co-

simulation interface being used. Some interfaces (e.g., PCI) are faster than others (e.g.,

JTAG). For a reasonably large design, the typical simulation is accelerated by an order of

magnitude when co-simulated in hardware.

Keeping the above points in mind, there are ways to further bolster simulation

performance. Remember that every time the PC interacts with hardware, there is an

overhead cost that impacts simulation performance. One of the ways the number of FPGA

transactions can be mitigated is by utilizing Simulink vector and frame signal types. Here

and throughout the rest of this tutorial, FPGA transactions involving Simulink vector and

frame signals as simply referred to as vector transfers. This idea is straightforward –

bundle as many input data samples together as possible and have the FPGA process the

data in a single transaction. Fewer transactions with the FPGA results in better simulation

performance.

In this tutorial, Simulink vector and frame signals are used to increase simulation

performance beyond what is traditionally possible with hardware co-simulation. A step-

by-step example filter design is presented to help illustrate these concepts.

Before diving into the details, it is worth exploring exactly what you are trying to

accomplish from a high-level perspective. In summary, you will do the following during a

Simulink simulation cycle:

• Buffer a series of scalar input data values into a Simulink vector;

• Transfer the vector data to a buffer residing on the FPGA using a burst transfer;

• Use the FPGA, in free-running clock mode, to sequentially process the entire input

buffer;

• Use the FPGA to write the data into an output buffer;

• Transfer the contents of the output buffer back into Simulink and reconstruct the data

as a Simulink vector;

• Unbuffer the vector into a series of output scalar values.

Shared Memories

Before a System Generator design can support vector transfers, it must be augmented with

appropriate input and output buffers. In hardware, these buffers are implemented using

internal memory (e.g., BRAMs) and are used to store vectors of simulation data that are

written to and read from the FPGA by the PC. This means that the maximum size of the

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