MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 161)

System Generator for DSP User Guide www.xilinx.com 161

UG640 (v 12.2) July 23, 2010

Integrating a Processor with Custom Logic

4. Comment out the software driver for the clock generator in the system.mss file

# BEGIN DRIVER

# PARAMETER DRIVER_NAME = generic

# PARAMETER DRIVER_VER = 1.00.a

# PARAMETER HW_INSTANCE = clock_generator_0

# END

5. After the modification, the clock generator is safely removed from the XPS project. You

can import this modified XPS project into System Generator through the single-clock

wiring scheme.

Caveats with Peripherals like UART and MDM

Peripherals like UART and MDM (microprocessor debugger module) do not work in the

single-stepped hardware co-simulation mode.

The UART peripheral needs to be driven by a specific input clock source in order to

communicate properly through the serial ports. If you choose a hardware co-simulation

frequency on the hardware co-simulation dialog box which is different from the clock

frequency with the original XPS project, you will see invalid output on the serial port

console.

For MDM, its connection with gdb will time out if its input clock frequency is too slow. In

this case, the debug session in SDK (Software Development Kit) or XMD (Xilinx

Microprocessor Debugger) will run into errors such as “Unable to stop MicroBlaze

processor.”

Troubleshooting

Limitations on the Imported XPS Project

In theory, any XPS project can be imported into System Generator through the EDK

Processor block. However, you may need to modify the XPS project in some situations to

avoid resource conflicts and to allow the EDK Processor block to properly interpret the

project.

• Input clock port: XPS uses

SIGIS = CLK to tag an external port as a clock port. The

EDK Processor block only recognizes a single input clock to implement the single

clock and dual clock wiring described above. In this case, you need to remove the

SIGIS = CLK tag on other clock ports. The following XPS project example has two

input clock ports,

sys_clk_pin and fpga_0_PCIe_Diff_Clk_IBUF_DS. In order to

import this project into System Generator, you need to ensure that

SIGIS = CLK is

removed from the PCI input clock ports.

PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I,

DIFFERENTIAL_POLARITY = P # need to remove SIGIS = CLK

PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I,

DIFFERENTIAL_POLARITY = N # need to remove SIGIS = CLK

• Resource conflict: You need to ensure that there is no resource conflict between the

imported XPS project and the rest of the System Generator design. For example, if you

use the Point-to-Point Ethernet-Based Hardware Co-Simulation flow and the target

hardware board has only one Ethernet MAC component (e.g., the Xilinx ML506,

SP601, and SP605 evaluation boards), the XPS project can contain peripherals that use

the Ethernet MAC (e.g., xps_ethernetlite). You should consider changing to the JTAG-

Based Hardware Co-Simulation flow in this case. Another example is when the target

hardware board only has a single BSCAN module (e.g., the Spartan 3A DSP 1800

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