MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 14)

14 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

A Brief Introduction to FPGAs

A field programmable gate array (FPGA) is a general-purpose integrated circuit that is

“programmed” by the designer rather than the device manufacturer. Unlike an

application-specific integrated circuit (ASIC), which can perform a similar function in an

electronic system, an FPGA can be reprogrammed, even after it has been deployed into a

system.

An FPGA is programmed by downloading a configuration program called a bitstream into

static on-chip random-access memory. Much like the object code for a microprocessor, this

bitstream is the product of compilation tools that translate the high-level abstractions

produced by a designer into something equivalent but low-level and executable. Xilinx

System Generator pioneered the idea of compiling an FPGA program from a high-level

Simulink model.

An FPGA provides you with a two-dimensional array of configurable resources that can

implement a wide range of arithmetic and logic functions. These resources include

dedicated DSP blocks, multipliers, dual port memories, lookup tables (LUTs), registers, tri-

state buffers, multiplexers, and digital clock managers. In addition, Xilinx FPGAs contain

sophisticated I/O mechanisms that can handle a wide range of bandwidth and voltage

requirements. The Virtex®-4 FPGAs include embedded microcontrollers (IBM PowerPC®

405), and multi-gigabit serial transceivers. The compute and I/O resources are linked

under the control of the bitstream by a programmable interconnect architecture that allows

them to be wired together into systems.

FPGAs are high performance data processing devices. DSP performance is derived from

the FPGA’s ability to construct highly parallel architectures for processing data. In contrast

with a microprocessor or DSP processor, where performance is tied to the clock rate at

which the processor can run, FPGA performance is tied to the amount of parallelism that

can be brought to bear in the algorithms that make up a signal processing system. A

combination of increasingly high system clock rates (current system frequencies of 100-200

Notes for Higher Performance

FPGA Design

Suggests design practices in System Generator that

lead to an efficient and high-performance

implementation in an FPGA.

Processing a System Generator

Design with FPGA Physical

Design Tools

Describes how to take the low-level HDL produced by

System Generator and use it in tools like Xilinx's

Project Navigator, ModelSim, and Synplicity's

Synplify.

Resetting Auto-Generated Clock

Enable Logic

Describes the behavior of rate changing blocks from

the System Generator library when the ce_clr signal

is used for re-synchronization.

Design Styles for the DSP48 Describes three ways to implement and configure a

DSP48 (Xtreme DSP Slice) in System Generator

Using FDATool in Digital Filter

Applications

Demonstrates one way to specify, implement and

simulate a FIR filter using the FDATool block.

Generating Multiple Cycle-True

Islands for Distinct Clocks

Describes how to implement multi-clock designs in

System Generator

Using ChipScope Pro Analyzer

for Real-Time Hardware

Debugging

Demonstrated how to connect and use the Xilinx

Debug Tool called ChipScope

™ Pro within System

Generator

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