MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 118)

118 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 1: Hardware Design Using System Generator

Generating Multiple Cycle-True Islands for Distinct Clocks

System Generator's shared memory interfaces allow you to implement designs that are

driven by multiple-clock sources. These multi-clock designs may employ a combination of

distinct clocks and derived clock enables to implement advanced clocking strategies

completely within a single design environment. This topic describes how to implement

multi-clock designs in System Generator through discussions of the following topics:

• Applications that benefit from multiple clocks;

• Using hierarchy to partition a System Generator model into two or more clock

domains;

• Using shared memories to cross clock domains;

• Simulating and netlisting multiple clock designs;

• Wiring multiple clock domains together using the Xilinx Multiple Subsystem

Generator block.

A step-by-step example is provided to help clarify the topics listed above. Although the

example uses two clocks, the concepts presented here can be extended so that System

Generator designs requiring any number of clock sources can be constructed using similar

techniques.

Before continuing with the example, you may want to familiarize yourself with standard

System Generator clocking terminology and implementation methodologies. This

information is covered in-depth in the topic Timing and Clocking. In general, System

Generator designs are driven by a single, system clock source. Multirate design portions

are handled using clock enables derived from the system clock source. It is possible,

however, to use System Generator to implement designs that are driven by distinct clock

sources.

Broadly speaking, the approach is the following:

Divide the design into several subsystems, each of which is to be driven by a different

clock. In the example, you call these subsystems asynchronous clock islands. Xilinx shared

memory blocks should be used as bridges that communicate between these clock islands.

Once the design is partitioned, the Xilinx Multiple Subsystem Generator block may be

used to translate the design into hardware that uses multiple distinct clock sources.

Multiple Clock Applications

A common application for multiple clock domains is for interfacing different pieces of

external hardware that operate at different clock rates. For example, you may need to

provide a set of I/O registers to a microprocessor, and the processor must be able to read

and write these registers synchronous to its own clock. You may get data from a clock/data

recovery unit and need to re-synchronize the data to your local clock domain. You may

need to feed data to a digital-to-analog converter that must be running at a precise sample

rate which is different from your system clock.

Another important application for multiple clock domains is in employing a high-speed

processing unit. Let us take an example of an interpolating FIR filter. The filter gets symbol

data from an external unit, and the filter needs to take the symbols and perform a 4X

interpolation that creates four output samples for each input symbol. The output samples

are fed to a digital-to-analog converter (DAC) that is clocked at the sample rate.

The FIR filter may be clocked at any of several rates. It may be clocked at the symbol rate,

and on each cycle it must create four samples which will then be fed to the DAC at the

sample rate. This highly parallel implementation has large hardware resource

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