MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 242)

242 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 3: Using Hardware Co-Simulation

Shared Memory Support

System Generator's hardware co-simulation interfaces allow shared memory blocks and

shared memory block derivatives (e.g., Shared FIFO and Shared Registers) to be compiled

and co-simulated in FPGA hardware. These interfaces make it possible for hardware-based

shared memory resources to map transparently to common address spaces on the host PC.

When applied to System Generator co-simulation hardware, shared memories can help

facilitate high-speed data transfers between the host PC and FPGA, and further bolster the

tool's real-time hardware co-simulation capabilities. This topic describes how shared

memories can be used within the context of System Generator's hardware co-simulation

framework.

Compiling Shared Memories for

Hardware Co-Simulation

Describes how to compile a System Generator

design for hardware co-simulation when the

design contains shared memory blocks.

Co-Simulating Unprotected

Shared Memories

Describes how shared memory blocks

configured with unprotected access mode

behave during hardware co-simulation.

Co-Simulating Lockable Shared

Memories

Describes how shared memory blocks

configured with lockable access mode behave

during hardware co-simulation.

Co-Simulating Shared Registers Describes how to compile a System Generator

design for hardware co-simulation when the

design contains shared Registers.

Co-Simulating Shared FIFOs Describes how to compile a System Generator

design for hardware co-simulation when the

design contains shared FIFOs.

Restrictions on Shared Memories Lists the restrictions that are imposed when

using shared memory blocks with hardware co-

simulation.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 242