290 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 3: Using Hardware Co-Simulation
d. If the LCD display does not show the information correctly, press the System
ACE™ Reset button to reconfigure the FPGA.
e. Check the status LEDs again to ensure the configuration sequence completed
successfully.
11. Verify the Ethernet Interface and Connection Status
a. Connect the Ethernet interface of the board to a network connection, or directly to
a host.
b. Check the on-board Ethernet status LEDs to make sure the Ethernet interface is
attached to an active Ethernet segment. The LEDs should reflect the link speed and
the duplex mode at which the interface is operating. The TX and RX leds should
flash on and off occasionally depending on the network traffic. If no LED is on,
press the CPU Reset button to reset the FPGA, and also examine whether the
Ethernet segment is active.
c. To ensure the board is reachable by the host, issue ICMP ping from the host to
check the connectivity. For example, type "ping 192.168.8.1" on a console to test the
connectivity to a board with IP address 192.168.8.1.
d. The target FPGA listens on the UDP port 9999. Please ensure the underlying
network does not block the associated traffic when network-based Ethernet
configuration is used. This does not affect point-to-point Ethernet configuration.
System ACE™ Reset
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