MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide download pdf (Page 154)

154 www.xilinx.com System Generator for DSP User Guide

UG640 (v 12.2) July 23, 2010

Chapter 2: Hardware/Software Co-Design

Asynchronous Support

Asynchronous support for processors allow for the processor and the accelerator hardware

hanging off the processor to be clocked with different clocks. This allows the hardware

accelerator to run at the fastest possible clock rate, or at a clock rate that is necessary for its

correct functioning, for example when it is required to interface with an external

peripheral.

This feature is enabled when the Dual Clock check box is selected in the EDK Processor

block GUI's Implementation tab. The figure below shows how clocks will be connected for

the import and export flow; in the export flow, the MicroBlaze ™(MB) block is not present.

Basically, the custom logic design in System Generator is driven with the clk clock and the

processor system is driven with the xps_clk clock. The clock source that drives the PLB bus

in the MicroBlaze processor system is extracted to drive the bus adaptor, the memory map,

and halves of the shared memories. Shared memories straddle between these two domains

(e.g. the clk domain and the plb_clock domain) and are driven by both these clocks. In the

import flow where an XPS project is imported into System Generator, the PLB bus on the

processor must be driven with the same clock as the xps_clk signal.

When Dual Clock is enabled and a design is netlisted for hardware co-simulation, a

slightly different clock wiring topology is used. This is shown in the figure below. The

clock source from the board is bifurcated with one branch going into the Hardware Co-

simulation module before being connected to the clk clock (depicted in the figure above).

The other branch is routed through a clock buffer and connected to the xps_clk clock

signal.

This topology allows for the custom logic designed in System Generator to be single-

stepped, while allowing the MicroBlaze processor to continue in free-running mode. This

allows for clock-sensitive peripherals (such as the RS232 UARTS) to work when the

Hardware Co-Simulation token is set to single-step.

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MATLAB DESIGN HDL CODER RELEASE NOTES User's Guide Page 154