MATLAB FIXED-POINT TOOLBOX - RELEASE NOTES User's Guide Page 92
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92 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 4: Getting Started
Additional Examples and Tutorials
Numerous examples are used to illustrate System Generator features and functions in the
System Generator documentaton. These examples are found in the directory at pathname
<ISE_Design_Suite_tree>/sysgen/examples and are listed in the table below. In
addition to these examples, System Generator also includes demonstration models that
can be run from the demo page. Enter the following command at the MATLAB prompt:
demo blocksets xilinx
Note:
If you are using the MATLAB help browser you can open and run the examples directly from
this page. To run an example, click on the link. MATLAB will change directories to the example
directory and open the example model.
Black Box Examples
ChipScope Examples
Topic Description
Importing a VHDL
Module
A tutorial showing how to use the black box to import VHDL into a
System Generator design and how to use ModelSim to co-simulate
the VHDL module.
Simulating Several
Black Boxes
Simultaneously
Shows how black boxes can co-simulate simultaneously, using only
one ModelSim license.
Dynamic Black Boxes A tutorial showing how to parameterize the black box.
Importing a Verilog
Module
A tutorial showing how to use the black box to import Verilog into
a System Generator design and how to use ModelSim to co-simulate
the Verilog module.
Importing a Xilinx
Core Generator
Module
A tutorial showing how to import a COREGEN module as a black
box.
Topic Description
Using ChipScope Pro
Analyzer for Real-
Time Hardware
Debugging
This tutorial demonstrates how to connect and use the Xilinx Debug
Tool called ChipScope
™ Pro within Xilinx System Generator for
DSP. The integration of ChipScope Pro in the System Generator flow
allows real-time debugging at system speed.
- Generator for 1
- Table of Contents 3
- Chapter 4: Getting Started 4
- About This Guide 7
- Additional Resources 8
- Conventions 8
- Online Document 9
- Preface: About This Guide 10
- Introduction 11
- The Xilinx DSP Block Set 12
- FIR Filter Generation 13
- Support for MATLAB 14
- System Resource Estimation 15
- Hardware Co-Simulation 16
- System Integration Platform 17
- Chapter 1: Introduction 18
- Installation 19
- Chapter 2: Installation 20
- Table 2-3: 20
- Table 2-4: 20
- UNC Paths Not Supported 21
- Software Prerequisites 21
- Post Installation Tasks 22
- UG639 (v 12.2) July 23, 2010 23
- ModelSim SE 24
- Setting the Size 25
- Setting the Number of Entries 25
- Release Information 27
- Hardware Recommendations 28
- Known Issues 29
- Release Notes 12.1 30
- Xilinx Blockset Enhancements 31
- Release Notes 11.4 35
- Table 3-5: 37
- Table 3-6: 37
- Release Notes 11.3 39
- Existing Block Updates 40
- Table 3-7: 41
- Table 3-8: 41
- Getting Started 43
- ® Simulator 44
- The Xilinx DSP Blockset 45
- Defining the FPGA Boundary 46
- Creating the DSP Design 48
- Generating the HDL Code 49
- Chapter 4: Getting Started 50
- DSP blockset 50
- Lesson 1 Summary 52
- Lab Exercise: Using Simulink 52
- Fixed-Point Numeric Precision 53
- Overflow and Round Modes 55
- Bit-Level Operations 56
- The Reinterpret Block 57
- The Convert Block 58
- The Concat Block 59
- Slice Block 60
- The BitBasher Block 61
- Lesson 2 Summary 62
- Lab Exercise: Signal Routing 62
- Lesson 3 - System Control 63
- The MCode Block 64
- State Machine Example 66
- The Expression Block 67
- Reset and Enable Ports 68
- Bursty Data 69
- Lesson 3 Summary 70
- Lab Exercise: System Control 70
- Lesson 4 - Multi-Rate Systems 71
- Up and Down Sampling Blocks 72
- Debugging Tools 75
- Sample Period “Rules” 76
- Lesson 5 - Using Memories 78
- Initializing RAMs and ROMs 79
- System Generator RAM Blocks 80
- System Generator ROM Blocks 81
- The Delay Block 82
- The FIFO Block 83
- Shared Memory Block 84
- Lab Exercise: Using Memories 85
- Lesson 6 - Designing Filters 86
- The Virtex DSP48 Math Slice 87
- FIR Compiler Block 88
- Using FDA Tool Coefficients 90
- Virtex®-5 architecture 91
- Black Box Examples 92
- ChipScope Examples 92
- DSP Examples 93
- M-Code Examples 94
- Processor Examples 94
- Shared Memory Examples 95
- Timing Analysis Examples 96
- Miscellaneous Examples 96
- System Generator Demos 97
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