MATLAB FIXED-POINT TOOLBOX - RELEASE NOTES User's Guide Page 39
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System Generator for DSP Getting Started Guide www.xilinx.com 39
UG639 (v 12.2) July 23, 2010
Release Notes 11.3
Release Notes 11.3
System Generator Enhancements
New Device Support
• Virtex®-6 Lower Power (Virtex-6 -1L)
• Virtex-6 HXT
• Virtex-5Q
New Platform Support
System Generator now supports JTAG HW co-simulation for the Spartan®-6 SP605
Platform
New Operating System Support
Full support for the following operating systems has been added:
• Windows Vista Business 32-bit (English)
• Red Hat Enterprise Desktop 5.2, 32 & 64-bit
• SUSE Linux Enterprise 10, 32 & 64-bit
Xilinx Blockset Enhancements
New Blocks
CIC Compiler 1.3
New block now available in System Generator with the following features:
• Supports Virtex
®-6 and Spartan®-6 FPGA devices
• Input and output streaming interface added for multiple channel implementations.
• Capability added to specify hardware over sampling specification as a sample period.
• Capability added to leverage over sampling factor to optimize resource utilization.
• nd (new data) input port is now only placed on the block when Sample Period is
selected as the format.
Note:
This block supersedes the CIC Compiler 1.2 block. The RATE_WE signal no longer acts as a
reset to the core, the core will update to the new rate on the next input sample, for a single channel
implementation, or the next input to the first channel, for multiple channel implementations.
Refer to the topic CIC Compiler 1.3for more information.
DDS Compiler 4.0
New block now available in System Generator with the following features:
• New option added to use the block as a Phase Generator or SIN/COS Lookup Table
only. This capability allows users to custom build a Direct Digital Synthesizer to fit
individual application needs.
• Increased Spurious Free Dynamic Range (SFDR) from 120 dB to 150 dB
- Generator for 1
- Table of Contents 3
- Chapter 4: Getting Started 4
- About This Guide 7
- Additional Resources 8
- Conventions 8
- Online Document 9
- Preface: About This Guide 10
- Introduction 11
- The Xilinx DSP Block Set 12
- FIR Filter Generation 13
- Support for MATLAB 14
- System Resource Estimation 15
- Hardware Co-Simulation 16
- System Integration Platform 17
- Chapter 1: Introduction 18
- Installation 19
- Chapter 2: Installation 20
- Table 2-3: 20
- Table 2-4: 20
- UNC Paths Not Supported 21
- Software Prerequisites 21
- Post Installation Tasks 22
- UG639 (v 12.2) July 23, 2010 23
- ModelSim SE 24
- Setting the Size 25
- Setting the Number of Entries 25
- Release Information 27
- Hardware Recommendations 28
- Known Issues 29
- Release Notes 12.1 30
- Xilinx Blockset Enhancements 31
- Release Notes 11.4 35
- Table 3-5: 37
- Table 3-6: 37
- Release Notes 11.3 39
- Existing Block Updates 40
- Table 3-7: 41
- Table 3-8: 41
- Getting Started 43
- ® Simulator 44
- The Xilinx DSP Blockset 45
- Defining the FPGA Boundary 46
- Creating the DSP Design 48
- Generating the HDL Code 49
- Chapter 4: Getting Started 50
- DSP blockset 50
- Lesson 1 Summary 52
- Lab Exercise: Using Simulink 52
- Fixed-Point Numeric Precision 53
- Overflow and Round Modes 55
- Bit-Level Operations 56
- The Reinterpret Block 57
- The Convert Block 58
- The Concat Block 59
- Slice Block 60
- The BitBasher Block 61
- Lesson 2 Summary 62
- Lab Exercise: Signal Routing 62
- Lesson 3 - System Control 63
- The MCode Block 64
- State Machine Example 66
- The Expression Block 67
- Reset and Enable Ports 68
- Bursty Data 69
- Lesson 3 Summary 70
- Lab Exercise: System Control 70
- Lesson 4 - Multi-Rate Systems 71
- Up and Down Sampling Blocks 72
- Debugging Tools 75
- Sample Period “Rules” 76
- Lesson 5 - Using Memories 78
- Initializing RAMs and ROMs 79
- System Generator RAM Blocks 80
- System Generator ROM Blocks 81
- The Delay Block 82
- The FIFO Block 83
- Shared Memory Block 84
- Lab Exercise: Using Memories 85
- Lesson 6 - Designing Filters 86
- The Virtex DSP48 Math Slice 87
- FIR Compiler Block 88
- Using FDA Tool Coefficients 90
- Virtex®-5 architecture 91
- Black Box Examples 92
- ChipScope Examples 92
- DSP Examples 93
- M-Code Examples 94
- Processor Examples 94
- Shared Memory Examples 95
- Timing Analysis Examples 96
- Miscellaneous Examples 96
- System Generator Demos 97
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